2017 恩智浦半导体校园招聘补招-研发类职位（上海/苏州）
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About the company:NXPSemiconductors N.V. (NASDAQ: NXPI) enables secure connections andinfrastructure for a smarter world, advancing solutions that make lives easier,better and safer. As the world leader in secure connectivity solutions forembedded applications, NXP is driving innovation in the secure connectedvehicle, end-to-end security & privacy and smart connected solutionsmarkets. Built on more than 60 years of combined experience and expertise, thecompany has 45,000 employees in more than 35 countries.
More information: www.nxp.com
How to apply:
Please send your CV our recruiters, specifying the positionyou’re applying to.
Shanghai position: emily.qian@nxp.com
Suzhou position: fiona.chen@nxp.com
Hot job:
1. Shanghai - IC Design Backend Engineer
2. Shanghai - IC Design andVerification Engineer
3. Shanghai – DFT (Design for Test)Engineer
4. Suzhou - Digital VerificationEngineer
5. Suzhou - Mix-Signal VerificationEngineer
6. Suzhou - Analog/Mixed Signal DesignEngineer
Shanghai – IC DesignBackend Engineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Work with the global design team to do complex SOC physicalimplementation for deep submicron design.
2. Participates in block level backend design for complex SOCdesigns.
3. Responsible for RTL to GDS flow including CPF definition,logic/physical synthesis, die size estimation, floor-planning, power planning,CTS, place and route, STA, signal integrity, timing closure, formalverification, DFM, DRC/LVS etc.
4. Play a critical role in high performance design timing closure.
Requirements:
1. Universitydegree in microelectronics engineering or equivalent, master degree or above ispreferred;
2. 2+ yearsindustry experience, at least 1 year in physical design role in submicronprojects;
3. Goodunderstanding on backend flow and process;
4. Successful completion of 2+ physical design projects (at least oneat 65nm or below);
5. Experience on Cadence, Synopsys, Magma, Mentor tools;
6. Hands onexperience on floorplan, place and route, STA, DRC/LVS;
7. Hands onexperience on synthesis, IR drop and signal integrity is preferred;
8. Goodcommunication skills is must, English language proficiency.
Shanghai - IC Design and VerificationEngineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Design and develop digital circuits for ARM core based SOCprojects and IPs.
2. Verification in module level and chip level, define and executeverification plan with full functional coverage.
3. Involved in the SoC level and Digital IP design and verification,and the SoC development for ARM based SoC projects.
4. Do RTL coding, integration and verification.
5. Do simulation in gate level, transistor level (full-chip spice).
6. Create function test patterns for testing engineering.
Requirements:
1. Bachelor or master degree in Microelectronics, Electronics,Electrical Engineering, Computer Science or relevant disciplines.
2. Good knowledge and have experience in digital circuitdesign/verification with Verilog/VHDL.
3. Can use the EDA tools from Cadence, Synopsys, or Mentor tools fordigital and/or analog developing.
4. Have knowledge about computer architecture, 8bit, 16bit or 32bitMicro-controller or Micro-processer is a plus.
5. Have knowledge on AMBA bus system is a plus.
6. Knowledge and experiences on verification and verificationmethodology is a plus.
7. Good language skill in English. Passed CET-6.
8. Have basic knowledge of VLSI design flow.
Shanghai – DFT(Design for Test) Engineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Design and integration DFT logic including SCAN, MBIST, JTAG,Boudary Scan etc
2. DFT strategy definition and implementation
3. Generate patterns for ATE and pattern support
4. Responsible for DFT related STA check or SDC delivery
5. Support silicon bringup
Requirements:
1. Universitydegree in microelectronics engineering or equivalent, master degree or above ispreferred;
2. 2+ yearsindustry experience, at least 1 year in physical design role in submicronprojects;
3. Goodunderstanding on backend flow and process;
4. Successfulcompletion of 2+ physical design projects (at least one at 65nm or below);
5. Experienceon Cadence, Synopsys, Magma, Mentor tools;
6. Hands onexperience on floorplan, place and route, STA, DRC/LVS;
7. Hands onexperience on synthesis, IR drop and signal integrity is preferred;
8. Goodcommunication skills is must, English language proficiency.
Suzhou - Digital Verification Engineer
Send CV tofiona.chen@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Main responsible on IP level, subsystem level and SoC levelverification for connectivity MCU, MPU which targets IoT application. theverification work includes develop test benches, modeling,assertions/checkers/monitors, test plan and test development and sign off fortape out.
2. Support the IP and SoC design, architecture definition.
3. Join the verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microelectronics,electronic engineering , computer science or relevant disciplines.
2. Good language skill in English, passed CET-6.
3. Have knowledge about EDA simulation and synthesis tool as well asVLSI design flow.
4. Good knowledge in Verilog, VHDL, System Verilog, and scriptlanguage.
5. Good knowledge in RTL code style, full synchronous design style,and knowledge of Design-for-Test (DFT) is a plus.
6. Complex IP/ SOC Design Verification, direct experience in IP/SOCor Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard(PCI-e, USB) is preferred.
7. Have used Unix/Linux system and EDA tool from Cadence, Synopsis,Mentor digital and/or analog development.
8. Have knowledge about computer architecture, 8bit, 16bit or 32bitMicro-controller or Micro-processer is a plus.
9. Have knowledge of OVM,VMM or UVM is a plus.
10. Have knowledge of Wireless communication ,DSP is a plus.
11. Prefer know-how of ARM or AHB bus system.
12. Prefer experience of formal verification with property scheme, forexample SVA (System Verilog Assertion).
Suzhou - Mix-Signal Verification Engineer
Send CV tofiona.chen@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Main responsible on IP level, subsystem level and SoC levelverification for connectivity MCU, MPU which targets IoT application. Defineand execute verification plan with full functional coverage.
2. Support the IP and SoC design, architecture definition.
3. Work on mixed signal simualtion on IP level,Sub- system level andSoC level.
4. Work on transistor level spice simulation for the SoC.
5. Join mix-signal verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microeletronics, electronicengineering , computer science or relevant disciplines.
2. [/color
2017 恩智浦半导体校园招聘补招-研发类职位（上海/苏州）
About the company:NXPSemiconductors N.V. (NASDAQ: NXPI) enables secure connections andinfrastructure for a smarter world, advancing solutions that make lives easier,better and safer. As the world leader in secure connectivity solutions forembedded applications, NXP is driving innovation in the secure connectedvehicle, end-to-end security & privacy and smart connected solutionsmarkets. Built on more than 60 years of combined experience and expertise, thecompany has 45,000 employees in more than 35 countries.
More information: www.nxp.com
How to apply:
Please send your CV our recruiters, specifying the positionyou’re applying to.
Shanghai position: emily.qian@nxp.com
Suzhou position: fiona.chen@nxp.com
Hot job:
1. Shanghai - IC Design Backend Engineer
2. Shanghai - IC Design andVerification Engineer
3. Shanghai – DFT (Design for Test)Engineer
4. Suzhou - Digital VerificationEngineer
5. Suzhou - Mix-Signal VerificationEngineer
6. Suzhou - Analog/Mixed Signal DesignEngineer
Shanghai – IC DesignBackend Engineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Work with the global design team to do complex SOC physicalimplementation for deep submicron design.
2. Participates in block level backend design for complex SOCdesigns.
3. Responsible for RTL to GDS flow including CPF definition,logic/physical synthesis, die size estimation, floor-planning, power planning,CTS, place and route, STA, signal integrity, timing closure, formalverification, DFM, DRC/LVS etc.
4. Play a critical role in high performance design timing closure.
Requirements:
1. Universitydegree in microelectronics engineering or equivalent, master degree or above ispreferred;
2. 2+ yearsindustry experience, at least 1 year in physical design role in submicronprojects;
3. Goodunderstanding on backend flow and process;
4. Successful completion of 2+ physical design projects (at least oneat 65nm or below);
5. Experience on Cadence, Synopsys, Magma, Mentor tools;
6. Hands onexperience on floorplan, place and route, STA, DRC/LVS;
7. Hands onexperience on synthesis, IR drop and signal integrity is preferred;
8. Goodcommunication skills is must, English language proficiency.
Shanghai - IC Design and VerificationEngineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Design and develop digital circuits for ARM core based SOCprojects and IPs.
2. Verification in module level and chip level, define and executeverification plan with full functional coverage.
3. Involved in the SoC level and Digital IP design and verification,and the SoC development for ARM based SoC projects.
4. Do RTL coding, integration and verification.
5. Do simulation in gate level, transistor level (full-chip spice).
6. Create function test patterns for testing engineering.
Requirements:
1. Bachelor or master degree in Microelectronics, Electronics,Electrical Engineering, Computer Science or relevant disciplines.
2. Good knowledge and have experience in digital circuitdesign/verification with Verilog/VHDL.
3. Can use the EDA tools from Cadence, Synopsys, or Mentor tools fordigital and/or analog developing.
4. Have knowledge about computer architecture, 8bit, 16bit or 32bitMicro-controller or Micro-processer is a plus.
5. Have knowledge on AMBA bus system is a plus.
6. Knowledge and experiences on verification and verificationmethodology is a plus.
7. Good language skill in English. Passed CET-6.
8. Have basic knowledge of VLSI design flow.
Shanghai – DFT(Design for Test) Engineer
Send CV toemily.qian@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Design and integration DFT logic including SCAN, MBIST, JTAG,Boudary Scan etc
2. DFT strategy definition and implementation
3. Generate patterns for ATE and pattern support
4. Responsible for DFT related STA check or SDC delivery
5. Support silicon bringup
Requirements:
1. Universitydegree in microelectronics engineering or equivalent, master degree or above ispreferred;
2. 2+ yearsindustry experience, at least 1 year in physical design role in submicronprojects;
3. Goodunderstanding on backend flow and process;
4. Successfulcompletion of 2+ physical design projects (at least one at 65nm or below);
5. Experienceon Cadence, Synopsys, Magma, Mentor tools;
6. Hands onexperience on floorplan, place and route, STA, DRC/LVS;
7. Hands onexperience on synthesis, IR drop and signal integrity is preferred;
8. Goodcommunication skills is must, English language proficiency.
Suzhou - Digital Verification Engineer
Send CV tofiona.chen@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Main responsible on IP level, subsystem level and SoC levelverification for connectivity MCU, MPU which targets IoT application. theverification work includes develop test benches, modeling,assertions/checkers/monitors, test plan and test development and sign off fortape out.
2. Support the IP and SoC design, architecture definition.
3. Join the verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microelectronics,electronic engineering , computer science or relevant disciplines.
2. Good language skill in English, passed CET-6.
3. Have knowledge about EDA simulation and synthesis tool as well asVLSI design flow.
4. Good knowledge in Verilog, VHDL, System Verilog, and scriptlanguage.
5. Good knowledge in RTL code style, full synchronous design style,and knowledge of Design-for-Test (DFT) is a plus.
6. Complex IP/ SOC Design Verification, direct experience in IP/SOCor Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard(PCI-e, USB) is preferred.
7. Have used Unix/Linux system and EDA tool from Cadence, Synopsis,Mentor digital and/or analog development.
8. Have knowledge about computer architecture, 8bit, 16bit or 32bitMicro-controller or Micro-processer is a plus.
9. Have knowledge of OVM,VMM or UVM is a plus.
10. Have knowledge of Wireless communication ,DSP is a plus.
11. Prefer know-how of ARM or AHB bus system.
12. Prefer experience of formal verification with property scheme, forexample SVA (System Verilog Assertion).
Suzhou - Mix-Signal Verification Engineer
Send CV tofiona.chen@nxp.com, specifying the position you’re applying to.
Responsibilities:
1. Main responsible on IP level, subsystem level and SoC levelverification for connectivity MCU, MPU which targets IoT application. Defineand execute verification plan with full functional coverage.
2. Support the IP and SoC design, architecture definition.
3. Work on mixed signal simualtion on IP level,Sub- system level andSoC level.
4. Work on transistor level spice simulation for the SoC.
5. Join mix-signal verification methodology innovation.
Requirements:
1. Bachelor or master degree, majoring in microeletronics, electronicengineering , computer science or relevant disciplines.
2. [/color
2017/3/29 17:51:34